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SC1189
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70C
Parameter Linear Sections Quiescent Current Output Voltage LDO1 Output Voltage LDO2 Gain (AOL) Load Regulation Line Regulation Output Impedance LDOV Undervoltage Lockout LDOEN Threshold LDOEN Sink Current Overcurrent Trip Voltage Power-up Output Short Circuit Immunity Output Short Circuit Glitch Immunity Gate Pulldown Impedance VOSENSE Impedance
Conditions
Min
Typ
Max
Units
LDOV = 12V 2.487 1.231 LDOS (1,2) to GATE (1,2) IO = 0 to 8A 2.525 1.250 90
5 2.563 1.269
mA V V dB
0.3 0.3
% % k V V A A % ms ms k k
VGATE = 6.5V 6.5 1.3 LDOEN = 3.3V LDOEN = 0V % of Vo set point 20 1 0.5 GATE (1,2) -AGND; VCC+BST=0V 80 10
1 8.0
1.5 10 1.9
0.01 -200 40 5 4 300
1.0 -300 60 60 30 750
Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recommendations.
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SC1189
POWER MANAGEMENT Pin Configuration
TOP VIEW
AGND GATE1 LDOS1 LDOS2 VCC PWRGD LDOEN CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID25MV VID0 VID1 VID2 VID3 VOSENSE EN BSTH BSTL DL
Ordering Information
Device (1) SC1189SWTR Package SO-24 Linear Voltage 1.25V/2.5V Temp Range (T J) 0 to 125C
Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices.
(24 Pin SOIC)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AGND GATE1 LDOS1 LDOS2 VCC PWRGD LDOEN CSCS+ PGNDH DH PGNDL DL BSTL BSTH EN
(1)
Pin Function Small Signal Analog and Digital Ground Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage Power Good Output, pulls low if VCC_CORE is outside valid range LDO Supply Monitor. Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter, High or open for normal operation Top end of internal feedback chain. Programming Input (MSB) Programming Input Programming Input Programming Input
VOSENSE VID3
(1)
VID2 (1) VID1 (1) VID0
(1) (1)
VID25MV LDOV GATE2
Programming Input (LSB) +12V for LDO section Gate Drive Output LDO2
Note: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1189
POWER MANAGEMENT Block Diagram
VCC CSCS+ EN
REF
CURRENT LIMIT
70mV
+ LEVEL SHIFT AND HIGH SIDE DRIVE
BSTH
VID3 VID2 VID1 VID0 VID25MV
D/A
ERROR AMP
+ -
DH
+
PGNDH
VOSENSE
R
+ -
OSCILLATOR S
Q
SHOOT-THRU CONTROL
PWRGD
OPEN COLLECTORS
+ AGND
BSTL
LDOEN LDOS1 GATE1
2.5V FET CONTROLLER REF 1.25V FET CONTROLLER
SYNCHRONOUS MOSFET DRIVE
DL
PGNDL
LDOV
GATE2
LDOS2
AGND
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SC1189
POWER MANAGEMENT Applications Information - Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0C < Tj < 85C
VID Parameter Output Voltage
(1)
Conditions IO = 2A in Application circuit
25MV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3210 0100 0100 0011 0011 0010 0010 0001 0001 0000 0000 1111 1111 1110 1110 1101 1101 1100 1100 1011 1011 1010 1010 1001 1001 1000 1000 0111 0111 0110 0110 0101 0101
Min 1.034 1.059 1.084 1.108 1.133 1.157 1.182 1.207 1.256 1.281 1.305 1.330 1.354 1.379 1.404 1.428 1.453 1.478 1.502 1.527 1.584 1.609 1.634 1.658 1.683 1.708 1.733 1.757 1.782 1.798
Typ 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825
Max 1.066 1.091 1.117 1.142 1.167 1.193 1.218 1.243 1.269 1.294 1.320 1.345 1.370 1.396 1.421 1.446 1.472 1.497 1.523 1.548 1.573 1.599 1.616 1.641 1.667 1.692 1.717 1.742 1.768 1.793 1.818 1.852
Units V
1.231 1.250
1.551 1.575
Note 1: VID[3:0] correspond to legacy VRM8.4 voltage levels for 1.3V to 1.8V
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SC1189
POWER MANAGEMENT Layout Guidelines
Careful attention to layout requirements are necessary for successful implementation of the SC1189 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency.
12V IN
5V
10 1 2 3 4 0.1uF 5 6 7 8 9 0.1uF 10 11 12
AGND GATE1 LDOS1 LDOS2 VCC PWRGD LDOEN CSCS+ PGNDH DH PGNDL GATE2 LDOV VID0 VID1 VID2 VID3 VID25MV VOSENSE EN BSTH BSTL DL
24 23 22 21 20 19 18 17 16 15 14 13 Q2 Cout L Q1 2.32k Cin + 1.00k 5mOhm Vout +
SC1189
3.3V Q3 + Cin Lin Cout Lin1 +
Vo Lin1
Heavy lines indicate high current paths.
Layout Diagram SC1189
Vo Lin2 Q4 Cout Lin2 +
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SC1189
POWER MANAGEMENT Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1189 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1189 should be supplied from the 5V supply through a 10 resistor, the Vcc pin should be decoupled directly to AGND by a 0.1F ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1189 should run parallel and close to each other. The 0.1F capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).
5V
Currents in Power Section
+ Vout +
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SC1189
POWER MANAGEMENT Component Selection
WITCHING S WITCHING SECTION CAPACITORS OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from:
R ESR Where Vt = Maximum transient voltage excursion It = Transient current step Vt It
and 0% duty cycle capability, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
ILRIPPLE = VIN 4 L fOSC
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Cap. Technology C (F) 330 330 1500 ESR (m) 60 25 44 Total ESR (m) 10 8.3 8.3
Ripple current allowance will define the minimum permitted inductor value. POWER POWER FETS - The FETs are chosen based on several criteria, with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
2 PCOND = IO RDS(on)
Qty. Rqd. C (F) 6 3 5
Low ESR Tantalum OS-CON Low ESR Aluminum
2000 990 7500
where = duty cycle VO VIN
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from:
L R ESR C VA It
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
PSW = IO VIN 10 -2
or more generally,
PSW = IO VIN ( t r + t f ) fOSC 4
where VA is the lesser of VO or (VIN - VO )
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = QRR VIN fOSC
The calculated maximum inductor value assumes 100%
To a first order approximation, it is convenient to only con-
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SC1189
POWER MANAGEMENT Component Selection (Cont.)
sider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type IRL34025 IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD (W) 1.69 1.19 2.26 Package D2Pak D2Pak S0-8
CAPACITORS INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. RESIST GATE RESISTOR SELECTION - The gate resistors for the top and bottom switching FETs limit the peak gate current and hence control the transition time. It is important to control the off time transition of the top FET, it should be fast to limit switching losses, but not so fast as to cause excessive phase node oscillation below ground as this can lead to current injection in the IC substrate and erratic behaviour or latchup. The actual value should be determined in the application, with the final layout and FETs. LIMIT, DROOP CURRENT SENSE, LIMIT, DR OOP AND OFFSET The converter is protected and it's loadline shaped by the signals generated from the sense resistor and associated components.
CURRENT LIMIT CIRCUIT
BOTT TTOM BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
2 PCOND = IO RDS( on) (1 - )
For the example above:
FET type IRL34025 IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD (W) 1.33 0.93 1.77 Package D2Pak D2Pak S0-8
V CS
Io
RD RF RS + Ra
VOSENSE
Each of the package types has a characteristic thermal impedance. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature Rise (OC) FET type IRL34025 IRL2203 Si4410 Top FET 67.6 47.6 180.8 Bottom FET 53.2 37.2 141.6
Vo
INDUCTOR
Rb Rc
DROOP AND OFFSET CIRCUIT
Rload
Current Limit, Droop and Offset circuit
Current Limit is given by IOLIM = VCS.(RD+RF)/(RS.RF) At no load the output voltage is given by: VO=VO(nom)*(1+(Ra.Rb)/(Rc*(Ra+Rb)) so the offset is: VOS=VO(nom)*1000*(Ra.Rb)/(Rc*(Ra+Rb)) and the droop is calculated as: VD=Io*RS*Rb/(Ra+Rb) where RS is in m, VOS and VD in mV For a full design procedure for droop and offset, see Application Note AN97-9, "Using Droop and Vout Offset for improved transient response".
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It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4.
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SC1189
POWER MANAGEMENT
FOLDBACK CURRENT LIMITING The SC1189 implements a "Hard Current Limit" overcurrent protection for the switching supply output. In a short circuit condition, this will lead to higher than normal power dissipation in the bottom side FETs. If this is problematic, foldback current limiting can be easily and inexpensively implemented to drastically reduce dissipation during output short circuit
RA RB To CS+ RC D1 1N4148
M=
IOLIM IOS M VB R D R F (M - 1)VCS (R D + R F )
3) Choose VB and calculate RB
RB =
4) Calculate the ratio of the input divider
RC V + VCS + VF =B (R A + R C ) VIN where VF = Forward Voltage drop of diode ( 0.6V)
VIN
VCS
To CS-
Choose RCRD
RF
L1
RS
VO
Output Current Path
Foldback current limit components
1
Breakpoint VOUT VB
0 0 IOS IOLIM 1
Foldback current limit characteristics
For a complete design procedure for foldback current limiting see Application Note AN01-2, "Foldback Current Limit". An abbreviated procedure is given below. 1) Choose values for IOLIM and RS and calculate the ratio
RF VCS = RD + RF IOLIM R S
If this ratio > 1, the value of RS or IOLIM must be increased. Then let RF=1kW and calculate RD. 2) Choose a short circuit current (IOS) and calculate M, do not be too agressive with M, a value between 2 and 3 should be sufficient. Choosing too low a value for IOS will result in a high value for M and may cause startup problems due to insufficient current.
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SC1189
POWER MANAGEMENT Theory of Operation (Linear OCP)
The Linear controllers in the SC1189 have built in Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on and the output currrent is RDS(ON) limited, this is detected by the gate voltage going very high while the output voltage is below approximately 40% of it's setpoint. To allow for capacitor charging and very short overcurrent durations, the gate voltage is ramped very slowly upwards whenever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reaching it's setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold values are exceeded, ensuring that there is sufficient gate drive capability and sufficient LDO input voltage capability. A block diagram of one LDO controller is shown below.
Gate 1.4V/us Vout 1V/ms Vout/2
Time
Startup with no short circuit
12V LDOV LDOEN
3.3V
If at some later time, a short circuit is applied to the output, the GATEx voltage will ramp up quickly as Vout falls to try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will continue ramping at the 1V/ms rate. If the short is not removed before the GATEx output reaches approximately LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO
Short applied
+ 10pF
C RAMP gm + + VREF 1.26V SWITCH CLOSED ON LOW + 10nA R R1 14uA S1 1.3V -
LDOV
GATEx
R2
1V/ms Gate
LDOV-0.7V
LDOSx
Vout
R
+
Vout Vout/2 Time
AGND
RESET BY LDOV LOW Q
Short circuit after startup
S + R LDOV-0.7V
If the LDO tries to start into a short, the gate ramps at the 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low.
During a normal start-up, once LDOV and LDOEN have reached their thresholds, the GATEx pin is released and CRAMP is charged by 10nA causing the GATEx voltage to ramp at 10nA/10pF = 1V/ms. Once the GATEx output has ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP threshold, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Vout, until Vout reaches setpoint and the loop settles into steady state regulation.
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Gate
LDOV-0.7V
1V/ms
Time
Startup into short circuit
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SC1189
POWER MANAGEMENT Typical Characteristics
Typical Efficiency (Switching section) Typical Ripple, Vo=1.75V, Io=10A
100%
PIN Descriptions
90% Efficiency
80%
1.75V 1.50V Vo=1.25V
70% 0 5 10 15 20 Output Current (A) 25 30
Transient Response Vo=1.75V, Io=0A to 28A
2.5V Linear Short circuit output response
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J2 12V D2 + R20 1k D1 1N4148 C27 OPEN TABLE VALID FOR 2x5mOhm SENSE RESISTOR R21 18k 1N4148 5V + 10 + R3 EMPTY 5
VCC LDOEN VID0 VID1 VID2 VID3 VID4 EN AGND LDOV GATE2 LDOS2 LDOS1 GATE1 PWRGD PGNDL PGNDH DL BSTL DH BSTH VOSENSE CSCS+
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C26 47uF R1 C18 1500uF + C19 1500uF + C1 0.1uF R22 390
POWER MANAGEMENT Typical Application Circuit
C2 1500uF C3 1500uF C4 0.1uF 9 8 17 15 11 14 13 10 12 6 2 3 J15 VCC_CORE PWRGD R2 10k 5V R12 1k R15 See Table 2 R11 See Table 2 C8 L1 C6 + 1.2uH + C9 C7 + + C10 0.1uF J17 Q3 IRL2203 R9 2R2 Q4 IRL2203 R10 2R2 R8 5mOhm Q1 IRL3103S R6 2R2 R19 5mOhm Q2 IRL3103S R7 2R2 0.1uF R4 1.00k R5 OPEN 7 22 21 20 19 18 16 1 S2 23 24 4 SC1189CS U1 C5
3.3V 3.3V COM 5V COM 5V COM PWR_OK 5VSB 12V 3.3V -12V COM PS_ON COM COM COM -5V 5V 5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ON/OFF
DROOP mV/A 0 1 2 5 1 2 5 1 2 5 OFFSET mV/V 0 2 2 2 5 5 5 10 10 10 R11 (Ohm) 0 3.3 10 EMPTY 8.3 25 EMPTY 16.7 50 EMPTY R15 (Ohm) EMPTY 5.0 2.5 2.0 12.5 6.3 5 25.0 12.5 10.0
ATX M/B MOLEX 39-29-9202
VID25MV
VID0
VID1
VCC_CORE
VID2
VID3
EN
5VSTBY
1 2 3 4
C28
C29
1500uF 1500uF 1500uF 1500uF
CON4
0.1uF
10uF
14
Q5 Q6 IRLR024N 5VSTBY R24 1k R23 442 3.3V STBY + 330uF Q9
PWRGD ADJGATE ADJSEN VTTSEL AGPSEL DELAY GND CAP+ CAPFC AGPSEN AGPGATE VTTSEN VTTGATE
J18 SCOPE TP
C11
+
+ C12
IRLR024N C20 + C22 + 2.5V + J14 Clock C16 C17 330uF + 330uF J24
VOUT
330uF
330uF
C21 + C23 +
J13 CHIPSET C15 + R27 1.00k R26 100k 2 6 7 4 R28 4.99k 5 3 C34 + 330uF 22nF SC1112CS J30 R29 10k C43 16 9 8 C33 0.1uF 10 C45 1uF IRFR120N 11 12 Q10 13 14 IRFR120N J27 CHIPSET 1.8V STBY
5VSTBY VTTIN
1.8V R25 100k 1 15 U2 Q8 IRFR120N
1500uF 1500uF 1500uF 1500uF
C14 330uF
VTT C31 0.1uF + C32 330uF AGP + C44 C46 0.1uF 330uF + C30 330uF
J26 1.25V/1.5V VTT
3.3V STBY C42 0.1uF
J28 J29 1.5V/3.3V AGP (2X/4X)
C35 C36 C37 C39 C40 330uF 330uF 330uF 0.1uF 0.1uF
C38 C41 330uF 0.1uF
+
+
+
+
J31
VID 25MV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VID 3210 0100 0100 0011 0011 0010 0010 0001 0001 0000 0000 1111 1111 1110 1110 1101 1101
VOUT VID 25MV 1.050 0 1.075 1 1.100 0 1.125 1 1.150 0 1.175 1 1.200 0 1.225 1 1.250 0 1.275 1 1.300 0 1.325 1 1.350 0 1.375 1 1.400 0 1.425 1
VID 3210 1100 1100 1011 1011 1010 1010 1001 1001 1000 1000 0111 0111 0110 0110 0101 0101
1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825
J32 J33 AGPSEL VTTSEL
VTTSEL = 1, VTTSEL = 0, AGPSEL = 1, AGPSEL = 0,
VTT = 1.5 V VTT = 1.25 V AGP=3.3V AGP=1.5V
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SC1189
SC1189
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 6 7 8 9 10 6 7 8 9 25 10 11 29 13 14 15 12 16 17 36 37 38 18 41 Qty. 12 12 14 1 1 1 1 2 1 1 2 2 2 3 1 2 2 4 2 2 3 1 1 1 2 1 1 1 Reference C1, C4, C5, C10, C28, C31, C33, C39, C40, C41, C42, C46 C2, C3, C6, C7, C8, C9, C18, C19, C20, C21, C22, C23 C11, C12, C14, C15, C16, C17, C30, C32, C34, C35, C36, C37, C38, C44 C26 C29 C43 C45 D1, D2 J2 L1 Q1, Q2 Q3, Q4 Q5, Q6 Q8,Q9,Q10 R1 R2, R29 R4, R27 R6, R7, R9, R10 R8, R19 R11, R15 R12, R20, R24 R21 R22 R23 R26, R25 R28 U1 U2
15
Value 0.1uF 1500uF 330uF 47uF 10uF 22nF 1uF 1N4148 ATX M/B 1.2uH IRLR3103S IRL2203 IRLR024N IRFR120N 10 10k 1.00k 2R2 5mOhm See Table 1k 18k 390 442 100k 4.99k SC1189CS SC1112CS
Notes
Low ESR Sanyo MV-GX or equivalent
MOLEX 39-29-9202 Panasonic PCC-S1
IRC OAR1
SEMTECH SEMTECH
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2004 Semtech Corp.
SC1189
POWER MANAGEMENT Outline Drawing - SO-24
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804
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